(c) 1996-2011 by H. Robbers @ Amsterdam the Netherlands

For those familiar with MC68000 family processors who desparately want
to go around any other way but cant.


SZ=00:B, 01:W, 10:L     defenitely NOT 11

column 1:
' ' = 68000 family
*   = higher than 68000
-   = Coldfire v4e ISA_C as extension or restriction
C   = Coldfire v4e ISA_C ONLY
#   = NOT Coldfire if otherwise family
1=68010/12, 2=68020, 3=68030, 4=68040, 6=68060, 5=68551, 8=68881,

S=privileged

A Coldfire instruction can never be longer than 6 bytes.
  Any combination of operands resulting in more than 2 extension words
  are invalid. This occurs mostly with the move instruction and floating
  point instructions.

Coldfire does NOT implement base and outer displacement.
Coldfire DOES implement scale facter for Xn.

<.....> = effective address:
 .....  = restrictions on addressing mode:
								 x: one octal digit for a register number
cntr	control					        2x       5x 6x 70 71 72 73
c_alt	control alterable		        2x       5x 6x 70 71
c_add	control addressable		        2x       5x 6x 70 71 72 73 74
m_alt	memory alterable		        2x 3x 4x 5x 6x 70 71
d_alt	data alterable			0x      2x 3x 4x 5x 6x 70 71
d_add	data addressable		0x      2x 3x 4x 5x 6x 70 71 72 73 74
m_add	memory addresing		        2x 3x 4x 5x 6x 70 71 72 73 74
alter	all alterable			0x 1xWL 2x 3x 4x 5x 6x 70 71
all								0x 1xWL 2x 3x 4x 5x 6x 70 71 72 73 74
+ 		includes (An)+
-		includes -(An)
D		includes Dn direct

addressing modes for <.....>
m0/m1	r0/r1
0		x		Dn
1		x		An
2		x		(An)
3		x		(An)+
4		x		-(An)+
5		x		d(An)
6		x		d(An,Xn)
7		0		nnnnn.W
		1		nnnnn.L
		2		d(PC)
		3		d(PC,Xn)
		4		#data

--- line 0 --------------------------------------------------------------------
					1	   0				1     0
					5432 109 876 543 210	54321098 76543210
						 r1  m1  m0  r0
#	ori  -> ccr		0000 000 000 111 100	00000000 ########	B
#S	ori  -> sr		0000 000 001 111 100	######## ########	W
	ori				0000 000 0SZ <d_alt>	#data				B,W,L
-	ori.l			0000 000 010 000 ddd	#data				L
C	bitrev			0000 000 011 000 ddd	#data				L
#	andi -> ccr		0000 001 000 111 100	00000000 ########	B
#S	andi -> sr		0000 001 001 111 100	######## ########	W
	andi			0000 001 0SZ <d_alt>	#data				B,W,L
-	andi.l			0000 001 010 000 ddd	#data				L
C	byterev			0000 001 011 000 ddd	#data				L
*	cmp2			0000 0SZ 011 <c_add>	Txxx0000 00000000
*	chk2			0000 0SZ 011 <c_add>	Txxx1000 00000000
	subi			0000 010 0SZ <d_alt>	#data				B,W,L
-	subi.l			0000 010 010 000 ddd	#data				L
C	ff1				0000 010 011 000 ddd	#data				L
	addi			0000 011 0SZ <d_alt>	#data				B,W,L
-	addi.l			0000 011 010 000 ddd	#data				L
2	callm			0000 011 011 <c_add>	00000000 ########
	btst  #n,ea		0000 100 000 <d_add>	00000000 ########
	bchg  #n,ea		0000 100 001 <d_alt>	00000000 ########
	bclr  #n,ea		0000 100 010 <d_alt>	00000000 ########
	bset  #n,ea		0000 100 011 <d_alt>	00000000 ########
#	eori -> ccr		0000 101 000 111 100	00000000 ########	B
#S	eori -> sr		0000 101 001 111 100	######## ########	W
	eori			0000 101 0SZ <d_alt>	#data				B,W,L
-	eori.l			0000 101 010 000 ddd	#data				L
	cmpi			0000 110 0SZ <d_add>	#data				B,W,L
-	cmpi			0000 110 0SZ 000 ddd	#data				B,W,L
*S	moves			0000 111 0SZ <m_alt>	txxxr000 00000000
*	cas				0000 1ss 011 <m_alt>	0000000u uu000ccc
											ss=01:B, 10:W, 11:L
*	cas2			0000 1ss 011 111 100		zie boek
											ss=      10:W, 11:L
#	movep			0000 xxx 1rm 001 aaa
	btst  Dn,ea		0000 xxx 100 <d_add>
	bchg  Dn,ea		0000 xxx 101 <d_alt>
	bclr  Dn,ea		0000 xxx 110 <d_alt>
	bset  Dn,ea		0000 xxx 111 <d_alt>

--- line 1,2,3-----------------------------------------------------------------
					1	   0				1     0
					5432 109 876 543 210	54321098 76543210
						 r1  m1  m0  r0
	move			00ss <d_alt> < all > 	ss=01: B, 11:W, 10:L
	movea			00ss aaa 001 < all >	ss=       11:W, 10:L

--- line 4 --------------------------------------------------------------------
					1	   0				1     0
					5432 109 876 543 210	54321098 76543210
						 r1  m1  m0  r0
	negx			0100 000 0SZ <d_alt>
-	negx.l			0100 000 010 000 ddd
S	move <- sr		0100 000 011 <d_alt>
-S  move <- sr		0100 000 011 000 ddd
C	stldsr			0100 000 011 100 111
					0100 011 011 111 100	######## ########
	clr				0100 001 0SZ <d_alt>
*	move <- ccr		0100 001 011 <d_alt>
-	move <- ccr		0100 001 011 000 ddd
	neg				0100 010 0SZ <d_alt>
-	neg.l			0100 010 010 000 ddd
	move -> ccr		0100 010 011 <d_add>
	not				0100 011 0SZ <d_alt>
-	not.l			0100 011 010 000 ddd
S	move -> sr		0100 011 011 <d_add>

*	link.l			0100 100 000 001 aaa	32 bit displ
	nbcd			0100 100 000 <d_alt>
	swap			0100 100 001 000 ddd
*	bkpt			0100 100 001 001 ###
	pea				0100 100 001 <contr>
	ext				0100 100 0ss 000 ddd	ss=10:W, 11:L
	movem ->mem		0100 100 01s <-c_alt>	mmmmmmmm mmmmmmmm	s=0:W,1:L
-	movem ->mem		0100 100 01s <c_alt>	mmmmmmmm mmmmmmmm
-*	extb.l			0100 100 111 000 ddd						(lea Dn,A4 :-)

	tst				0100 101 0SZ <d_alt>
*	tst				0100 101 0SZ < all >
C	halt			0100 101 011 001 000
C	pulse			0100 101 011 001 100
	tas				0100 101 011 <d_alt>
	illegal			0100 101 011 111 100
											 D            D
-	mulu.l			0100 110 000 <d_add>	0lll0000 00000000   32bit to lll
*	mulu.l			0100 110 000 <d_add>	0lll0s00 00000hhh   s=0:32bit to lll, s=1:64bit to hhh:lll
-	muls.l			0100 110 000 <d_add>	0lll1000 00000000
*	muls.l			0100 110 000 <d_add>	0lll1s00 00000hhh
-	divu.l			0100 110 001 <d_add>	0qqq0000 00000qqq

*	divul.l			0100 110 001 <d_add>	0qqq0000 00000rrr
C	remu.l			0100 110 001 <d_add>	0qqq0000 00000rrr

*	divu.l			0100 110 001 <d_add>	0qqq0100 00000rrr
-	divs.l			0100 110 001 <d_add>	0qqq1000 00000qqq

*	divsl.l			0100 110 001 <d_add>	0qqq1000 00000rrr
C	rems.l			0100 110 001 <d_add>	0qqq1000 00000rrr

*	divs.l			0100 110 001 <d_add>	0qqq1100 00000rrr
C	sats  			0100 110 010 000 ddd
	movem ->reg		0100 110 01s <c_add+>	mmmmmmmm mmmmmmmm	s=0:W,1:L
-	movem ->reg		0100 110 01s <c_add>	mmmmmmmm mmmmmmmm

	trap			0100 111 001 00# ###
	link			0100 111 001 010 aaa	dddddddd dddddddd
	unlk			0100 111 001 011 aaa
S	move An,usp		0100 111 001 100 aaa
S	move usp,An		0100 111 001 101 aaa
S	reset			0100 111 001 110 000
	nop				0100 111 001 110 001
S	stop			0100 111 001 110 010	######## ########
S	rte				0100 111 001 110 011
*	rtd				0100 111 001 110 100	dddddddd dddddddd
	rts				0100 111 001 110 101
#	trapv			0100 111 001 110 110
#	rtr				0100 111 001 110 111
2	rtm	Dn			0100 111 001 110 ddd
*S	movec Rc,Rn		0100 111 001 111 010	txxxcccc cccccccc
-*S	movec Rn,Rc		0100 111 001 111 011	txxxcccc cccccccc
2	rtm	An			0100 111 001 111 aaa
	jsr				0100 111 010 <c_add>
	jmp				0100 111 011 <c_add>

*	chk.l			0100 xxx 100 <d_add>
#	chk.w			0100 xxx 110 <d_add>
	lea				0100 aaa 111 <contr>

--- line 5 --------------------------------------------------------------------
					1	   0				1     0
					5432 109 876 543 210	54321098 76543210
						 r1  m1  m0  r0
	addq			0101 ### 0SZ <alter>
-	addq.l			0101 ### 010 <alter>
	subq			0101 ### 1SZ <alter>
-	subq.l			0101 ### 110 <alter>
#	dbcc			0101 cccc 11 001 ddd	dddddddd dddddddd
	scc				0101 cccc 11 <d_alt>
-	scc				0101 cccc 11 000 ddd
C	tpf  			0101 0001 11 111 mmm	#data			  B?,W,L
*	trapcc.w #		0101 cccc 11 111 010    ######## ########
*	trapcc.l #		0101 cccc 11 111 011	32 bit data
*	trapcc			0101 cccc 11 111 100
					1	   0				1     0
--- line 6 --------------------------------------------------------------------
					5432 1098  7654 3210	54321098 76543210
	bra.b			0110 0000  dddd dddd
	bra.w			0110 0000  0000 0000	dddddddd dddddddd
-*	bra.l			0110 0000  1111 1111	32 bits displ
	bsr.b			0110 0001  dddd dddd
	bsr.w			0110 0001  0000 0000	dddddddd dddddddd
-*	bsr.l			0110 0001  1111 1111	32 bits displ
	bcc.b			0110 cccc  dddd dddd
	bcc.w			0110 cccc  0000 0000	dddddddd dddddddd
-*	bcc.l			0110 cccc  1111 1111	32 bits displ
--- line 7 --------------------------------------------------------------------
	moveq			0111 ddd0  #### ####
C	mvs				0111 ddd 10s <d_add>	s= word, s= long
C	mvz				0111 ddd 11s <d_add>	s= word, s= long

--- line 8 --------------------------------------------------------------------
					1	   0				1     0
					5432 109 876 543 210	54321098 76543210
						 r1  m1  m0  r0
	or   ea,Dn		1000 ddd 0SZ <d_add>
-	or.l ea,Dn		1000 ddd 010 <d_add>
	divu			1000 ddd 011 <d_add>
#	sbcd Dx,Dy		1000 yyy 100 000 ddd
#	sbcd -(Ax),-(Ay)1000 yyy 100 001 aaa
*	pack Dx,Dy		1000 yyy 101 000 ddd	jjjjjjjj jjjjjjjj
*	pack -(Ax),-(Ay)1000 yyy 101 001 aaa	jjjjjjjj jjjjjjjj
*	unpk Dx,Dy		1000 yyy 110 000 ddd	jjjjjjjj jjjjjjjj
*	unpk -(Ax),-(Ay)1000 yyy 110 001 aaa	jjjjjjjj jjjjjjjj
	or   Dn,ea		1000 ddd 1SZ <m_alt>
-	or.l Dn,ea		1000 ddd 110 <m_alt>
	divs			1000 ddd 111 <d_add>

--- line 9 --------------------------------------------------------------------
						 r1  m1  m0  r0
	sub	  ea,Dn		1001 ddd 0SZ < all >
-	sub.l ea,Dn		1001 ddd 010 < all >
#	suba.w			1001 aaa 011 < all >
	subx   Dx,Dy	1001 yyy 1SZ 000 ddd
-	subx.l Dx,Dy	1001 yyy 110 000 ddd
#	subx -(Ax),-(Ay)1001 yyy 1SZ 001 aaa
	sub	  Dn,ea		1001 ddd 1SZ <m_alt>
-	sub.l Dn,ea		1001 ddd 110 <m_alt>
	suba.l			1001 aaa 111 < all >

--- line A --------------------------------------------------------------------
						 r1  m1  m0  r0
#	Linea			1010 ### ### ### ###	Line_a emulator
C	move3q #d,ea	1010 ### 101 <d_alt>

C	MAC...		beyond the scope of this document

--- line B --------------------------------------------------------------------
					1	   0				1     0
					5432 109 876 543 210	54321098 76543210
						 r1  m1  m0  r0
	cmp	  ea,Dn		1011 ddd 0SZ < all >
	cmpa.w			1011 aaa 011 < all >
	cmpm			1011 xxx 1SZ 001 yyy
	eor	  Dn,ea		1011 ddd 1SZ <d_alt>				(cmp Dn,ea misused)
-	eor.l Dn,ea		1011 ddd 110 <d_alt>
	cmpa.l			1011 aaa 111 < all >

--- line C --------------------------------------------------------------------
	and	  ea,Dn		1100 ddd 0SZ <d_add>
-	and.l ea,Dn		1100 ddd 010 <d_add>
	mulu			1100 ddd 011 <d_add>
#	abcd Dx,Dy		1100 yyy 100 000 ddd
#	abcd -(Ax),-(Ay)1100 yyy 100 001 aaa
	and	  Dn,ea		1100 ddd 1SZ <m_alt>
	and.l Dn,ea		1100 ddd 110 <m_alt>
	muls			1100 ddd 111 <d_add>
#	exg  Dx,Dy		1100 xxx 101 000 yyy
#	exg  Ax,Ay		1100 xxx 101 001 yyy
#	exg  Dx,Ay		1100 xxx 110 001 yyy

--- line D --------------------------------------------------------------------
	add   ea,Dn		1101 ddd 0SZ < all >
-	add.l ea,Dn		1101 ddd 010 < all >
#	adda.w			1101 aaa 011 < all >
	addx   Dx,Dy	1101 yyy 1SZ 000 ddd
-	addx.l Dx,Dy	1101 yyy 110 000 ddd
#	addx -(Ax),-(Ay)1101 yyy 1SZ 001 aaa
	add   Dn,ea		1101 ddd 1SZ <m_alt>
-	add.l Dn,ea		1101 ddd 110 <m_alt>
	adda.l			1101 aaa 111 < all >

--- line E --------------------------------------------------------------------
	asl,asr #,Dn	1110 ### rSZ 000 ddd	shifts: r=0:right,1=left
	lsl,lsr			1110 ### rSZ 001 ddd
-	asl,asr #,Dn	1110 ### r10 000 ddd
-	lsl,lsr			1110 ### r10 001 ddd
#	roxl,roxr		1110 ### rSZ 010 ddd
#	rol,ror			1110 ### rSZ 011 ddd

	asl,asr Dx,Dy	1110 xxx rSZ 100 yyy
	lsl,lsr			1110 xxx rSZ 101 yyy
-	asl,asr Dx,Dy	1110 xxx r10 100 yyy
-	lsl,lsr			1110 xxx r10 101 yyy
#	roxl,roxr 		1110 xxx rSZ 110 yyy
#	rol,ror			1110 xxx rSZ 111 yyy

#	asl,asr <ea>	1110 000 r11 <m_alt>	B
#	lsl,lsr			1110 001 r11 <m_alt>	B
#	roxl,roxr		1110 010 r11 <m_alt>	B
#	rol,ror			1110 011 r11 <m_alt>	B

*	bftst			1110 100 011 <Dc_add>	0000dooo ooDwwwww
*	bfextu			1110 100 111 <Dc_add>	0xxxdooo ooDwwwww
*	bfchg			1110 101 011 <Dc_alt>	0000dooo ooDwwwww
*	bfexts			1110 101 111 <Dc_add>	0xxxdooo ooDwwwww
*	bfclr			1110 110 011 <Dc_alt>	0000dooo ooDwwwww
*	bfffo			1110 110 111 <Dc_add>	0xxxdooo ooDwwwww
*	bfset			1110 111 011 <Dc_alt>	0000dooo ooDwwwww
*	bfins			1110 111 111 <Dc_alt>	0xxxdooo ooDwwwww

--- line F --------------------------------------------------------------------

The Coldfire only knows coprocessor 1, the floating point set.
Coldfire floating point doesnt implement size x (12 bytes)

					1	   0				1     0
					5432 109 876 543 210	54321098 76543210
						 r1  m1  m0  r0
35S	ploadr			1111 000 000 <c_alt>	00100010 000FFFFF zie boek
35S	ploadw			1111 000 000 <c_alt>	00100000 000FFFFF zie boek
5	pvalid VAL,ea	1111 000 000 <c_alt>	00101000 00000000	"
5	pvalid (An),ea	1111 000 000 <c_alt>	00101100 00000rrr	"
3S	pflush			1111 000 000 <c_alt>	001mmm00 MMMFFFFF	"
5S	pflush			1111 000 000 <c_alt>	001mmm0M MMMFFFFF	"
3S	pmove ea,MRn	1111 000 000 <c_alt>	010ppp00 00000000 for srp,crp&tc
3S	pmove.. MRn,ea	1111 000 000 <c_alt>	010ppp1f 00000000 		"
											011000r0 00000000 for mmusr
											000010rf 00000000 for TT0
											000011rf 00000000 for TT1
												   f = 1: .. = fd

5S	pmove			1111 000 000 < ')  >	010pppr0 00000000 for tc,drp,srp,
															  crp,cal,val,scc,
															  ac
											011pppr0 000num00 for bad,bac
											011pppr0 00000000 for psr,pcsr
					') r=1: alter, r=0: all

35S	ptest			1111 000 000 <c_alt>	100lllra xxxFFFFF
5S	pflushr			1111 000 000 <m_add>	10100000 00000000	"

5S	pdbcc			1111 000 001 001 ddd	00000000 00cccccc
5S	pscc			1111 000 001 <d_alt>	00000000 00cccccc
5S	ptrapcc			1111 000 001 111 ooo	00000000 00cccccc
5S	pbcc.w			1111 000 010 ccc ccc	dddddddd dddddddd
5S	pbcc.l			1111 000 011 ccc ccc	32 bit displ
5S	psave			1111 000 100 <-c_alt>
5S	prestore		1111 000 101 <c_add+>

*8S fsave			1111 001 100 <-c_alt>
*8S frestore		1111 001 101 <c_add+>

very special are:
*8 fmovem ea,m		1111 001 000 <c_add+>	110-0000 mmmmmmmm
*8 fmovem ea,Dn		1111 001 000 <c_add+>	110-1000 0ddd0000
*8 fmovem m,ea		1111 001 000 <-c_alt>	111+0000 mmmmmmmm
*8 fmovem Dn,ea		1111 001 000 <-c_alt>	111+1000 0ddd0000
					1	   0				1     0
					5432 109 876 543 210	54321098 76543210
						 r1  m1  m0  r0
CS	intouch			1111 010 000 101 aaa	zie book
46S	cinv			1111 010 0cc 0sc aaa		"
46S	cpush			1111 010 0cc 1sc aaa		"
3S	pflusha			1111 000 000 <c_alt>	0010 010 000 000 000
3S	pflush			1111 000 000 <c_alt>	001m mm0 0xx xff fff
46S	pflush			1111 010 100 0oo aaa	zie book
4S	ptestw			1111 010 101 001 aaa        "
4S	ptestr			1111 010 101 101 aaa        "
6S	plpa			1111 010 11r 001 aaa        "

46	move16 (Ay)+,L	1111 011 000 000 yyy	32 bit address
46	move16 L,(Ay)+	1111 011 000 001 yyy	32 bit address
46	move16 (Ay),L	1111 011 000 010 yyy	32 bit address
46	move16 L,(Ay)	1111 011 000 011 yyy	32 bit address
46	move16 Ax+,Ay+	1111 011 000 100 xxx	1yyy0000 00000000

6S	lpstop			1111 100 000 000 000	00000001 11000000 #### #### #### ####

General coprocessor instructions:
23	cpGEN			1111 cpi 000 <.....>	command&extensions
23	cpDBcc			1111 cpi 001 001 ddd	00000000 00cccccc
23	cpScc			1111 cpi 001 <d_alt>	00000000 00cccccc
23	cpTRAPcc		1111 cpi 001 111 ooo	00000000 00cccccc + word|long
23	cpBcc.w			1111 cpi 010 ccc ccc
23	cpBcc.l			1111 cpi 011 ccc ccc
23S cpSAVE			1111 cpi 100 <-c_alt>
23S cpRESTORE		1111 cpi 101 <c_add+>

On the 68040, 68060 and Coldfire the following floating point opcodes
have the fs.... and fd.... variants:
				s		d
fabs	0x18	0x58	0x5c
fadd	0x22	0x62	0x66
fdiv	0x20	0x60	0x64
fmove	0x00	0x40	0x44
fmul	0x23	0x63	0x67
fneg	0x1a	0x5a	0x5e
fsqrt	0x04	0x41	0x45
fsub	0x28	0x68	0x6c
